Introducing the Verilog HDL in a brief format, this book presents a selected set of the changes the popular hardware underwent in its first revision—emerging as IEEE Std 1364-2001 or Verilog-2001. It addresses the main features that support the design of combinational and sequential logic, and emphasizes synthesizable models, with a limited discussion of the theoretical framework for synthesis. Chapter topics cover an Introduction to Digital Design Methodology; Basic Concepts: Primitives, Data Types, and Operators in Verilog; Modeling Structure with Verilog; Modeling Behavior with Verilog; and Modeling Finite-State Mechanics and Datapath Controllers with Verilog. For designers with no backgrounds in HDLs, and designers familiar with Verilog 1995 and interested in the new features of Verilog 2001.
